Using PLLs in Quartus II Software

Phase-locked loops (PLLs) in the Stratix® device series and Cyclone™ device series are enabled in the Quartus® II software by using the altpll megafunction. The available ports on the altpll megafunction vary depending on the device family and PLL type.

In Stratix II and Cyclone II devices, the altclkctrl megafunction can be used to implement a basic clock control block which allows the user to:

  • Specify the operation mode of the clock control block
  • Choose the number of input clock sources
  • Provide an active high clock enable control input


Additional information about the altpll and altclkctrl megafunctions can be found in the following user guides:

altpll Megafunction User Guide (version 2.0, Feb. 2003, 1,099 KB)
Clock Control Block (altclkctrl) Megafunction User Guide (version 2.4, Dec. 2008, 337 KB)