This megafunction is used to implement the clock power down and clock source selection features.
This megafunction is used to implement phase-locked loops (PLLs) and the features they support.
This feature allows the PLL to automatically switch between two reference input clocks and can be used for clock redundancy or for a dual clock domain application. When the primary clock signal is not present the clock switchover circuitry automatically switches from the primary to the secondary clock for the PLL input clock reference.
The bandwidth of a PLL is the measure of the PLL’s ability to track the input clock and jitter. The closed-loop gain 3-dB frequency of the PLL determines the PLL bandwidth. The bandwidth is approximately the unity gain point for the PLL open loop response.
A high bandwidth PLL provides a fast lock time and tracks jitter on the reference clock source, passing it through to the PLL output. A low bandwidth PLL filters out reference clock jitter, but increases lock time.
Bank skew is the amount of time difference between the outputs in a particular I/O bank with a single input driving the outputs as shown in Figure 1.