Why does the port "sta_hd_altpe3_hip_core_top_hd_altpe3_hip_core_u_clkmux_core_clk_cnt_reg_0_0_q" generated in the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* Verilog file is different from the port name in the EDA netlist?

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.4 and earlier, you may see a case mismatch between the Verilog HDL file generated for the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* and the EDA netlist.

Verilog HDL file: sta_hd_altpe3_hip_core_top_hd_altpe3_hip_core_u_clkmux_core_clk_cnt_reg_0_0_q

<Intel® Quartus® installation folder>/quartus/eda/sim_lib/twentynm_hip_atoms.v: sta_hd_altpe3_hip_core_top_hd_altpe3_hip_core_u_clkmux_core_clk_cnt_reg_0_0_Q

To work around this problem, edit the port name to "sta_hd_altpe3_hip_core_top_hd_altpe3_hip_core_u_clkmux_core_clk_cnt_reg_0_0_q"

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition version 20.1.