Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools

Last Modified: November 16, 2020
Version Found: v20.3
Bug ID: 1508510367, 1508510010

Why do accesses transceiver reconfiguration registers fail when connecting the interface to another Avalon-MM master in Platform Designer?


Due to a problem in the Intel® Quartus® Prime Pro Edition software, accesses to  transceiver reconfiguration registers may fail when connecting the reconfiguration interface to another Avalon-MM master in Platform Designer. The interface default Read Latency is incorrectly set to '0', which doesn't match transceiver reconfiguration interface behavior. 

This problem exists in multiple transceiver related IPs, e.g. Transceiver Native PHY Intel Arria® 10/Cyclone® 10 FPGA IP, Intel Arria 10/Cyclone 10 Hard IP for PCI Express, Intel Stratix 10 E-Tile Transceiver Native PHY, L-Tile/H-Tile Transceiver Native PHY, Intel L-/H-Tile Avalon streaming for PCI Express. 


To work around this problem, modify the Read Latency of the reconfiguration interface to '1' manually.         

This problem is scheduled to be fixed in future release of the Intel® Quartus® Prime Pro Edition software.