Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools

Last Modified: October 07, 2020
Version Found: v20.1
Version Fixed: v20.3
Bug ID: 1508227182

Internal Error: Sub-system: LAB, File: /quartus/legality/lab/lab_nd_config_creator_module.cpp, Line: 1062 An illegal ALE was detected.


Due to a problem in the Intel® Quartus® Prime Pro edition software version 20.1 and 20.2, you may see this internal error during the fitter stage.This problem only occurs in designs targeting eSRAM Intel® Stratix® 10 FPGA IP.


To work around this problem, perform the following actions

1. open /esram_1914/synth/_1914_<>.sv

2. find the c0_sd_n_0_reg signal and remove the altera_attribute as follows.   

    (before)           (* altera_attribute = "-name FORCE_HYPER_REGISTER_FOR_UIB_ESRAM_CORE_REGISTER ON"*)  logic  c0_sd_n_0_reg/* synthesis dont_merge */;   

    (after)                 logic  c0_sd_n_0_reg/* synthesis dont_merge */;

3. repeat same changes for all other signals for c1_sd_n_0_reg to c7_sd_n_0_reg if you use other eSRAM channels.


This problem is fixed beginning with version 20.3 of the Intel® Quartus® Prime Pro edition software.