Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools

Last Modified: June 18, 2019
Version Found: v19.1
Bug ID: 1507225795

Why are the Output Enable/Disable Times for a bus the minimum value for all bits of the bus?


Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1, the Output Enable/Disable Times reports the minimum delays instead of displaying the maximum value for bus bits. This problem occurs when targeting Intel® Stratix® 10 devices.  


To work around this problem, expand the aggregated data bus bits and identify the maximum delay value manually.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.