Device Family: Intel® Arria® 10

Intel Software: Intel FPGA SDK for OpenCL

Type: Answers

Area: Tools

Last Modified: July 09, 2019
Version Found: v17.1 Update 2
Bug ID: 1507286731

Why do I see the hold timing violation in DCP1.2 OpenCL BSP design?


You may see a small hold timing violation when you compile a DCP1.2 OpenCL BSP design.



This hold timing violation does not cause any functional issue on DCP1.2 OpenCL BSP design.

This timing violation will be fixed in a future release of the DCP OpenCL BSP design.