Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.3, you may see this internal error during the synthesis stage of compilation when none of PLL reference clock input is connected. This problem occurs when compiling for Intel® Stratix® 10 devices.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Last Modified: December 16, 2019
Version Found: v19.3
Bug ID: 1608808775