Due to a problem in Intel® Quartus® Prime Pro software version 18.0 or earlier, when a partition is placed in a row clock region adjacent to the Transceiver Bank in one project (or in developer project) and is reused using the QDB_FILE_PARTITION assignment into another project (or into consumer project) you may see the following Internal Error:
Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/altera_arch_common/altera_arch_re_network_routing_constraints.cpp
- A clock sector defined by the green box in Figure. 1
- A row clock region is half-clock sector wide and one LAB row tall represented by the red dotted box in Figure. 1.
- In the consumer project, if the reused partition has a placement in this region, you may see the above Internal Error.