Why does the Intel® Stratix® 10 Single Port RAM show Don’t care value instead of Old data for read during write?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 17.1 and earlier, you will see incorrect behavior in simulation for read during write to an Intel Stratix 10 single port RAM with following parameters settings.

altera_syncram_component.intended_device_family = "Stratix 10"

altera_syncram_component.operation_mode = "SINGLE_PORT"

altera_syncram_component.read_during_write_mode_port_a = "OLD_DATA"

altera_syncram_component.ram_block_type = "M20K"

This is only a simulation issue, you will not see this on hardware.

Workaround/Fix

To work around this problem, run the post-synthesis / post-fit netlist simulation instead of functional simulation.

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro Edition software.

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