You may see this error if your design contains a chained DSP instance with more DSP blocks than there are in a spine clock region in your device.
Designs such as custom FIR filters connect DSP blocks together with the scan or chain buses. The number of DSP blocks that can be connected with the scan or chain buses is limited.
The limit on the number of DSP blocks in a chain varies by device and is based on the number of DSP blocks in a column of a spine clock region. To determine this limit, perform the following steps:
- Run Synthesis/Analysis on your design
- Open Chip Planner and select "Spine Clock Regions" in the Layers Settings tab. For example, the Intel® Arria® 10 10AX066 is divided into 30 spine clock regions as shown below: