Device Family: Intel® Arria® 10, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools

Last Modified: August 08, 2018
Version Found: v18.0
Bug ID: FB: 574317;

Error(170079): Cannot place node of type DSP block 


You may see this error if your design contains a chained DSP instance with more DSP blocks than there are in a spine clock region in your device.

Designs such as custom FIR filters connect DSP blocks together with the scan or chain buses.  The number of DSP blocks that can be connected with the scan or chain buses is limited. 

The limit on the number of DSP blocks in a chain varies by device and is based on the number of DSP blocks in a column of a spine clock region. To determine this limit, perform the following steps:

  • Run Synthesis/Analysis on your design
  • Open Chip Planner and select "Spine Clock Regions" in the Layers Settings tab.  For example, the Intel® Arria® 10 10AX066 is divided into 30 spine clock regions as shown below:



  • Zoom in to one of the Spine Clock Regions.  Each spine clock region may have 1, 2, or 4 DSP columns.  The number of DSP blocks and DSP columns varies in each spine clock region.  For example, see image below of spine clock region 15 in Intel® Arria® 10 10AX066 with 4 columns where the 2 longer columns have 31 DSP blocks and the 2 shorter columns have 27 DSP blocks.


In the Intel® Arria® 10 10AX066, the number of DSP blocks per spine clock column is as follows:

1 column of 19 DSP blocks

40 columns of 27 DSP blocks

8 columns of 28 DSP blocks

8 columns of 30 DSP blocks

4 columns of 31 DSP blocks

Total Columns: 61

Total DSP Blocks: 1687

If your design calls for instantiation of multiple chained DSP instances, then select the number of blocks appropriately.  27 DSP blocks chained will fit in almost all spine clock regions of the Intel® Arria® 10 10AX066. 

The Fitter will select the best available spine clock region for your design.


To avoid this error, make sure the number of DSP blocks in the chain does not exceed the number DSP blocks in a spine clock region column.