Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1 and earlier, you may see this internal error in the fitter plan stage when compiling a Intel® Stratix® 10 design with multiple instances of the ALTCLKCTRL Intel® FPGA IP. This error occurs when the clock gating feature is enabled and drives logic within a single IO bank or transceiver tile.
Only one clock gate is supported within a single IO Bank or transceiver tile in Intel® Stratix® 10 devices.