Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools

Version Found: v18.1
Bug ID: FB: 605811;

Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen7_fpp_design_manager.cpp, Line: 529


Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1 and earlier, you may see this internal error in the fitter plan stage when compiling a Intel® Stratix® 10 design with multiple instances of the ALTCLKCTRL Intel® FPGA IP. This error occurs when the clock gating feature is enabled and drives logic within a single IO bank or transceiver tile.

Only one clock gate is supported within a single IO Bank or transceiver tile in Intel® Stratix® 10 devices.



To avoid the error reduce the number of clock control blocks with clock gating feature enabled within a single IO Bank or transceiver tile to one.

This configuration is scheduled to provide a clear error message in a future release of the Intel® Quartus® Prime Pro edition software.