How do I set Verilog HDL macros from the command line using Quartus Prime Pro edition software?

The Quartus® Prime Pro Edition Handbook does not list a method for setting a Verilog HDL macro in the "quartus_syn" command.  

To set Verilog HDL macros at the command line in quartus_syn, use the following format:

quartus_syn <PROJECT_NAME> --set=VERILOG_MACRO <"VERILOG_MACRO_NAME= VALUE">

For example, the following command:

quartus_syn my_project --set=VERILOG_MACRO "a=2"

The command above has the same effect as specifying:

'define a 2       // in a Verilog HDL source file

Please note, this command will add the following additional line to your Quartus Settings File (.qsf) :

set_global_assignment -name VERILOG_MACRO "a=2"

If you don't want the the *.qsf to have this line added, then add this option to the quartus_syn command:

--write_settings_files=off