Article ID: 000080386 Content Type: Error Messages Last Reviewed: 08/30/2023

Error (19169): Transfer between periphery and DSP or RAM will make timing transfer impossible.

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This error is expected for Intel® Stratix® 10. This is because the Intel® Stratix®10 device only supports transfer to and from the periphery using a core Flip-Flop (FF) and look-up table (LUT).

Resolution

The workaround is to add the FF or LUT between the periphery.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs