Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools

Last Modified: September 18, 2017
Version Found: v17.0
Bug ID: FB: 492640;
IP: Shift Register (RAM-based)

Why do I get error “either synchronous clear option or clock enable option can be chose at the same time” in Platform Designer generation with Stratix 10


Due to a problem in the Quartus® Prime Pro software version 17.1 with Stratix® 10 device, you may see the Shift Register (RAM Based) IP Parameter Editor Pro error out message mentioned above in the Platform Designer generation. This happened whenever you try to instantiate both synchronous clear port and clock enable port together.


To work around the problem, disable either the synchronous clear port or the clock enable port.

This restriction will be lifted in a future release of the Quartus Prime Pro software.