Due to a problem in the Quartus® Prime Pro software version 17.1 with Stratix® 10 device, you may see the Shift Register (RAM Based) IP Parameter Editor Pro error out message mentioned above in the Platform Designer generation. This happened whenever you try to instantiate both synchronous clear port and clock enable port together.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
To work around the problem, disable either the synchronous clear port or the clock enable port.
This restriction will be lifted in a future release of the Quartus Prime Pro software.