Type: Answers, Errata

Area: EMIF, Intellectual Property

Compilation Failure with UniPHY Cores Targeting Arria V and Cyclone V


For DDR2 and DDR3 interfaces targeting Arria V or Cyclone V devices with the Enable Hard External Memory Interface parameter turned on and the Enable Configuration and Status Register Interface parameter turned on, your design may fail in compilation with an error similar to the following:

Error: Can't route signal "dut:inst|dut_0002:dut_inst|dut_p0:p0| dut_p0_acv_hard_memphy:umemphy|csr_afi_cal_success" to atom "dut:inst|dut_0002:dut_inst|dut_p0:p0|dut_p0_acv_hard_memphy: umemphy|dut_p0_phy_csr:phy_csr_inst|csr_register_0004[24]".

This issue will be fixed in a future version of the DDR2 and DDR3 SDRAM Controller with UniPHY.


In a text editor, open the RTL file submodules/<name>_p0_acv_hard_memphy.v

In the above file, change the following lines:

assign csr_afi_cal_success = afi_cal_success;� assign csr_afi_cal_fail = afi_cal_fail;


assign csr_afi_cal_success = io_intaficalsuccess;� assign csr_afi_cal_fail = io_intaficalfail;