For DDR2 and DDR3 interfaces targeting Arria V or Cyclone V devices with the Enable Hard External Memory Interface parameter turned on and multiple port front end widths as shown in the following table, a correction factor is needed.
This issue may cause your design to fail in simulation. This issue affects DDR2 and DDR3 interfaces targeting the hard memory interface resources on Arria V or Cyclone V devices. This issue will be fixed in a future version of the DDR2 and DDR3 SDRAM Controller with UniPHY.
|Multi-Port Front-End Width||Correction Required|