Type: Answers, Errata

Area: EMIF, Intellectual Property



Incorrect Multiple Port Address Width

Description

For DDR2 and DDR3 interfaces targeting Arria V or Cyclone V devices with the Enable Hard External Memory Interface parameter turned on and multiple port front end widths as shown in the following table, a correction factor is needed.

This issue may cause your design to fail in simulation. This issue affects DDR2 and DDR3 interfaces targeting the hard memory interface resources on Arria V or Cyclone V devices. This issue will be fixed in a future version of the DDR2 and DDR3 SDRAM Controller with UniPHY.

Address Widths Requiring Correction

Total Memory Interface Width

8

32

-1

8

64

-2

8

128

-3

8

256

-4

16

64

-1

16

128

-2

16

256

-3

32

32

+1

32

128

-1

32

256

-2

40

160

-1

40

320

-2

Multi-Port Front-End Width Correction Required

Workaround/Fix

The workaround for this issue is as follows:

  1. In a text editor, open the file altera_mem_if_hard_memory_controller_top(arriav/cyclonev).sv.
  2. In altera_mem_if_hard_memory_controller_top(arriav/cyclonev).sv, add the following lines after // New parameters for HMC:
  3. parameter AVL_ADDR_WIDTH_PORT_0 = AVL_ADDR_WIDTH <\'Correction needed\' - value> ; parameter AVL_ADDR_WIDTH_PORT_1 = AVL_ADDR_WIDTH <\'Correction needed\' - value> ; parameter AVL_ADDR_WIDTH_PORT_2 = AVL_ADDR_WIDTH <\'Correction needed\' - value> ; parameter AVL_ADDR_WIDTH_PORT_3 = AVL_ADDR_WIDTH <\'Correction needed\' - value> ; parameter AVL_ADDR_WIDTH_PORT_4 = AVL_ADDR_WIDTH <\'Correction needed\' - value> ; parameter AVL_ADDR_WIDTH_PORT_5 = AVL_ADDR_WIDTH <\'Correction needed\' - value> ;
  4. In altera_mem_if_hard_memory_controller_top(arriav/cyclonev).sv, replace AVL_ADDR_WIDTH with the respective AVL_ADDR_WIDTH_PORT_#, for example:
  5. Replace input [AVL_ADDR_WIDTH - 1 : 0] avl_addr_0;

    with

    input [AVL_ADDR_WIDTH_PORT_0 - 1 : 0] avl_addr_0;
  6. In altera_mem_if_hard_memory_controller_top(arriav/cyclonev).sv, comment out the lines from assign i_avst_cmd_data_0 = i_avst_cmd_data_g[0];
  7. until

    assign avl_size_g[5] = avl_size_5;
  8. In altera_mem_if_hard_memory_controller_top(arriav/cyclonev).sv, add the following lines immediately after the section above:
  9. assign i_avst_cmd_data_0 = {{42-AVL_SIZE_WIDTH-34{1\'b0}},avl_size_0,{34-AVL_ADDR_WIDTH_PORT_0-2{1\'b0}},avl_addr_0,avl_write_req_0,avl_read_req_0}; assign i_avst_cmd_data_1 = {{42-AVL_SIZE_WIDTH-34{1\'b0}},avl_size_1,{34-AVL_ADDR_WIDTH_PORT_1-2{1\'b0}},avl_addr_1,avl_write_req_1,avl_read_req_1}; assign i_avst_cmd_data_2 = {{42-AVL_SIZE_WIDTH-34{1\'b0}},avl_size_2,{34-AVL_ADDR_WIDTH_PORT_2-2{1\'b0}},avl_addr_2,avl_write_req_2,avl_read_req_2}; assign i_avst_cmd_data_3 = {{42-AVL_SIZE_WIDTH-34{1\'b0}},avl_size_3,{34-AVL_ADDR_WIDTH_PORT_3-2{1\'b0}},avl_addr_3,avl_write_req_3,avl_read_req_3}; assign i_avst_cmd_data_4 = {{42-AVL_SIZE_WIDTH-34{1\'b0}},avl_size_4,{34-AVL_ADDR_WIDTH_PORT_4-2{1\'b0}},avl_addr_4,avl_write_req_4,avl_read_req_4}; assign i_avst_cmd_data_5 = {{42-AVL_SIZE_WIDTH-34{1\'b0}},avl_size_5,{34-AVL_ADDR_WIDTH_PORT_5-2{1\'b0}},avl_addr_5,avl_write_req_5,avl_read_req_5};
  10. In altera_mem_if_hard_memory_controller_top(arriav/cyclonev).sv, comment out the following line:
  11. i_avst_cmd_data_g[port_i] = {avl_size_g[port_i],{34-AVL_ADDR_WIDTH-2{1\'b0}},avl_addr_g[port_i],avl_write_req_g[port_i],avl_read_req_g[port_i]};
  12. In all wrappers that instantiate the altera_mem_if_hard_memory_controller_top(arriav/cyclonev).sv, update the bus width for each avl_addr_<port>, as follows:
  13. Replace input wire [21:0] avl_addr_0, // .address

    with

    input wire [21<\'Correction needed\' value>:0] avl_addr_0, // .address