Type: Answers, Errata

Area: EMIF, Intellectual Property



Unexpected Timing Results in Design With Both ALTMEMPHY and UniPHY

Description

Projects using both DDR3 SDRAM Controller with ALTMEMPHY and QDR II/II+ SRAM Controller with UniPHY in the same design may experience unexpected timing results.

This issue will be fixed in a future version of the DDR3 SDRAM Controller with ALTMEMPHY and the QDR II/II+ SRAM Controller with UniPHY.

Workaround/Fix

The workaround for this issue is to ensure that the project’s .qsf file lists the .sdc file for the DDR3 SDRAM Controller with ALTMEMPHY above the .sdc file for the QDR II/II+ SRAM Controller with UniPHY.