Type: Answers

Type: Errata

Area: EMIF

Area: Intellectual Property



Self-refresh Not Working Properly for Single-rank DDR3 DIMMs

Description

The self-refresh feature does not work properly in simulation or in hardware, for DDR3 registered DIMM designs having Number of chip selects set to 1 and Enable Self-Refresh Control enabled.

This issue will be fixed in a future version of the DDR2 and DDR3 SDRAM Controller with UniPHY.

Workaround/Fix

Open the alt_mem_if_nextgen_ddr3_controller_core.v or alt_mem_if_ddr3_controller_top.sv file in an editor and change the following line:

.MEM_IF_CKE_WIDTH (MEM_IF_CS_WIDTH),

to

.MEM_IF_CKE_WIDTH (CTL_CS_WIDTH),