Simulating with the VCS Simulator

The DDR and DDR2 SDRAM High-Performance Controller MegaCore functions do not fully support the VCS simulator.

This issue affects all configurations.

The design does not simulate.

The following workarounds exist.

For VHDL change the following code:

• In file <variation name>_example_driver.vhd, change all when statements between lines 333 and 503 from when std_logic_vector’(“<bit_pattern>”) to when “<bit_pattern>”.
• In file testbench\<example name>_tb, change line 191 from signal zero_one(gMEM_BANK_BITS -1 downto 0) := (0 => ‘1’, others => ‘0’) to signal zero_one(gMEM_BANK_BITS -1 downto 0) := (\'1\', others=> \'0\').

For Verilog HDL:

No changes are necessary. Calls to the Verilog analyzer sets the v2k switch to enable Verilog 2000 constructs.

�This issue will be fixed in a future version of the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP.