Type: Answers, Errata

Area: EMIF, Intellectual Property



VHDL Simulation Fails When DDR CAS Latency 2.0 or 2.5 Is Selected

Description

VHDL generated sequencer block for CAS latency 2.0 and 2.5 designs using DDR SDRAM High-Performance Controller results in simulation failure. The issue is due to delta cycle delays on a clock net.

This issue affects DDR SDRAM High-Performance Controller CAS latency 2.0 and 2.5 designs.

This issue only affects simulation on VHDL and does not affect the functionality of the design.

Workaround/Fix

To work around this issue, follow these steps:

  1. Open the <variation_name>_phy.vho file in the project directory.
  2. Search for the altsyncram instantiation for the postamble block (this can be done by searching for " altsyncram" —note the white space). This should be the altsyncram component with a label that includes the word "postamble".
  3. Search for the signal that is attached to the clock1 port to find the point in the design where this signal is assigned to (in a test case, this is on line 4043).
  4. wire_<variation_name>_phy_<variation_name>_phy_alt_mem_phy_sii_<variation_name>_phy_alt_mem_phy_sii_inst_<variation_name>phy_alt_mem_phy_postamble_sii_poa_altsyncram_half_rate_ram_gen_altsyncram_inst_19557_clock1
  5. Change the assignment as shown. The signal inside not(..) should be the same as the signal on clock0 port of a second instance of the altsyncram component which is associated to the read datapath (with "read_dp" in the label).
  6. wire_<variation_name>_phy_<variation_name>_phy_alt_mem_phy_sii_<variation_name>_phy_alt_mem_phy_sii_inst_<variation_name>_phy_alt_mem_phy_postamble_sii_poa_altsyncram_half_rate_ram_gen_altsyncram_inst_19557_clock1 <= not (wire_<variation_name>_phy_<variation_name>_phy_alt_mem_phy_sii_<variation_name>_phy_alt_mem_phy_sii_inst_<variation_name>_phy_alt_mem_phy_clk_reset_sii_clk_<variation_name>_phy_alt_mem_phy_pll_sii_pll_19462_c4);

    This step removes a delta delay for simulation but leaves the code unchanged. The right side of the assignment above is taken as the right side of the assignment to the signal which is previously assigned to the "wire_<variation_name>_phy_<variation_name>_phy_alt_mem_phy_sii_<variation_name>_phy_alt_mem_phy_sii_inst_<variation_name>_phy_alt_mem_phy_postamble_sii_poa_altsyncram_half_rate_ram_gen_altsyncram_inst_19557_clock1" signal.

  7. If the <variation_name>_phy component is recompiled in your simulator, the design should now pass.

This issue will be fixed in a future version of the DDR SDRAM Controller with ALTMEMPHY IP.