Type: Answers, Errata
Area: EMIF, Intellectual Property
The example testbench RTL simulation may not simulate correctly when a dedicated memory clock phase is selected because clock net delay between the PLL and the clock output pins is not modelled in the RTL.
This issue affects designs that enable the Use dedicated PLL outputs to drive memory clocks option and set a value for the Dedicated memory clock phase parameter.
The design does not simulate correctly.
Add MEM_CLK_DELAY to clk_to_ram signal
at example top-level testbench, to compensate for the on-chip clock
net delay to mem_dqs which is not present in the RTL
simulation.
parameter DED_MEM_CLK = 1;
parameter real DED_MEM_CLK_PHASE = <value for dedicated
memory clock phase>
parameter real mem_clk_ratio = ((360.0DED_MEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = mem_clk_ratio*CLOCK_TICK_IN_PS
* (DED_MEM_CLK 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
//Replace testbench clk_to_ram assignment by adding MEM_CLK_DELAY
//assign clk_to_ram = clk_to_sdram[0];
This issue will be fixed in a future version of the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP.