Type: Answers, Errata

Area: EMIF, Intellectual Property

Postamble Calibration Scheme in Sequencer Violates Timing


For DDR memory interfaces with low frequency, the postamble calibration scheme in the sequencer violates the refresh memory timing parameter, breaching the JEDEC specifications.

This issue affects all designs with DDR SDRAM controller using the following frequencies and devices:

  • Frequency between 110 and 120 MHz for Arria II GX devices.
  • Frequency between 100 and 110 MHz for Stratix II devices.
  • Frequency below 133 MHz frequency for Stratix III and Stratix IV devices.

Your design fails to simulate.


Reduce the initial postamble latency by performing the following steps:

  1. Open <variation name>_phy_alt_mem_phy.v file.
  2. Search for the POSTAMBLE_INITIAL_LAT parameter.
  3. Subtract a few cycles off from the current value.

This issue will be fixed in a future version of the DDR SDRAM Controller with ALTMEMPHY IP.