The maximum clock rate for Cyclone III speed grades supporting full-rate DDR2 SDRAM on column I/Os are downgraded for version 9.1 and later. The maximum clock rate is downgraded because the Quartus II tool is unable to achieve push-button placement at the faster clock rates with DDR2 SDRAM high-performance controller II (HPC II).
table shows the downgraded specifications for the Quartus II software version 9.1.
|Memory Standard||Device||Speed Grade||Maximum Full-Rate Clock Rate (MHz)|
|Column I/O (Single Chip Select)|
This issue affects all designs that use full-rate DDR2 SDRAM with HPC II architecture and target the Cyclone III devices. If you are using DDR2 SDRAM with HPC architecture, you are not affected by this downgrade.
There is no design impact.