Type: Answers, Errata

Area: EMIF, Intellectual Property



Address Mirroring Not Supported by Memory Simulation Model

Description

This issue affects multiple chip select DDR3 DIMMs which require mirrored address bits; this issue can cause your design to fail in simulation.

The default memory simulation model does not support address mirroring. When you generate your design in the example testbench with the address mirroring parameter enabled, your simulation fails. To simulate successfully, you must replace the current memory simulation model with a vendor memory model and mirror the address bits in the <variation_name>_example_top_tb.v or .vhd file.

Workaround/Fix

Use the vendor memory model and mirror the address bits in the example top for target chip selects by doing the folowing:

  1. Regenerate the DDR3 testbench. After regenerating the testbench, in the top variant file, <variation_name>.v or .vhd, look for the following code:
  2. //Retrieval info: <PRIVATE name = “use_generated_memory_model” value=”true” type=”STRING” enable=”1”/>

    and change the code to the following:

    //Retrieval info: <PRIVATE name = “use_generated_memory_model” value=”false” type=”STRING” enable=”1”/>

  3. Download the vendor memory model.
  4. For the chip selects that require address monitoring, edit the <variation_name>_example_top_tb.v or .vhd file by performing the following:
  5. Add the following lines:

    wire[gMEM_ADDR_BITS - 1:0] a_reversed; wire[gMEM_BANK_BITS - 1:0] ba_reversed; assign a_reversed[2:0] = a_delayed[2:0]; assign a_reversed[3] = a_delayed[4]; assign a_reversed[4] = a_delayed[3]; assign a_reversed[5] = a_delayed[6]; assign a_reversed[6] = a_delayed[5]; assign a_reversed[7] = a_delayed[8]; assign a_reversed[8] = a_delayed[7]; assign a_reversed[gMEM_ADDR_BITS - 1:9] = a_delayed[gMEM_ADDR_BITS - 1:9]; assign ba_reversed[0] = ba_delayed[1]; assign ba_reversed[1] = ba_delayed[0]; assign ba_reversed[gMEM_BANK_BITS - 1:2] = ba_delayed[gMEM_BANK_BITS - 1:2];

    Locate the following lines:

    .ba (ba_delayed), .addr (a_delayed[14-1: 0]),

    and change to:

    .ba (ba_reversed), .addr (a_reversed),