In QDR II and QDR II+ SRAM Controllers with UniPHY targeting
Arria V or Cyclone V devices, with read latency not equal to 2,
the complimentary clock
mem_cq_n is not used for capture,
therefore the pin is unused.
In cases where read latency equals 2,
as the capture clock and
mem_cq is unused.
This issue affects QDR II and QDR II+ SRAM Controllers targeting Arria V and Cyclone V devices, where read latency does not equal 2.