ECC and CSR Designs Fail Timing

For designs created with the high-performance controller II (HPC II) version 11.0 or later, and configured with the Enable Configuration and Status Register Interface or Enable Error Detection and Correction Logic options enabled, the ECC and CSR elements will fail timing in the Quartus II software.

The workaround for this issue is as follows:

1. Create a new SDC file in your project.
2. Add the following lines to your SDC file: set_multicycle_path -from [get_keepers {*csr_*}] -to [get_keepers {*}] -setup -end 2 set_multicycle_path -from [get_keepers {*csr_*}] -to [get_keepers {*}] -hold -end 2
3. Add the SDC file to your project by clicking Add/Remove Files in Project from the Project menu.

This issue will be fixed in a future version of the DDR2 and DDR3 SDRAM Controller with UniPHY.