Article ID: 000082999 Content Type: Troubleshooting Last Reviewed: 11/24/2011

Non-leveled DDR2 Topology Fails Timing with Stratix V Devices for DDR2 and DDR3 SDRAM Controller with UniPHY

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    A non-leveled topology does not work with the DDR2 protocol targeting Stratix V. devices.

    Resolution

    There is no workaround for this issue.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs