Type: Answers, Errata

Area: EMIF, Intellectual Property



Erroneous Timing Failures in Designs Containing Both UniPHY and ALTMEMPHY Instantiations for External Memory Interfaces

Description

Designs containing both UniPHY and ALTMEMPHY instantiations may encounter erroneous clock failures during timing analysis.

Workaround/Fix

The workaround for this issue is to open the UniPHY <core_name>_report_timing.tcl and <core_name>_pin_map.tcl files in an editor, and make the following change in each file:Locate the traverse_to_ddio_out_pll_clock function name, and append the numeral 2 to the function name, making it traverse_to_ddio_out_pll_clock2.