Article ID: 000076604 Content Type: Troubleshooting Last Reviewed: 11/18/2011

VHDL-Generated Fileset Can Encounter Synthesis Problems for UniPHY External Memory Interfaces

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    An error in the VHDL-generated wrapper for the synthesis fileset can result in a variety of synthesis problems.

    Resolution

    The workaround for this issue is to open the generated wrapper file in a text editor, and replace all ports of the form std_logic_vector(0 downto 0) with std_logic .

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices