Device Family: Stratix® V

Type: Answers, Errata

Area: EMIF, Intellectual Property

Stratix V QDR II and QDR II+ SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY Memory Interfaces May Exhibit Write Timing Failure


Memory interfaces targeting Stratix V devices may exhibit write setup or write hold timing failures.


A workaround for interfaces running at 400MHz or slower is to enable the high-performance Nios II-based sequencer instead of the RTL-based sequencer.