Type: Answers, Errata

Area: EMIF, Intellectual Property



Simulation Fails for Memory Additive CAS Latency Settings > 0

Description

For DDR2 or DDR3 with UniPHY designs created with a version of the high-performance controller II (HPC II) earlier than 11.0, choosing a value greater than zero for the Memory additive CAS latency option on the Memory Parameters tab in the parameter editor may cause the design to fail in simulation.

Workaround/Fix

The workaround for this issue is to add the MEM_ADD_LAT parameter to the dut.v� wrapper file that instantiates the controller wrapper (alt_mem_if_ddr*_controller_top.sv), so that MEM_ADDLAT is passed down to the� controller wrapper.