For DDR2 or DDR3 with UniPHY designs created with a version of the high-performance controller II (HPC II) earlier than 11.0, choosing a value greater than zero for the Memory additive CAS latency option on the Memory Parameters tab in the parameter editor may cause the design to fail in simulation.
Type: Answers, Errata
Area: EMIF, Intellectual Property
The workaround for this issue is to add the
dut.v� wrapper file that instantiates the controller
alt_mem_if_ddr*_controller_top.sv), so that
passed down to the� controller wrapper.