How to Use UniPHY-based Memory IP with SOPC Builder

A workaround is necessary to enable UniPHY-based memory IP support with SOPC Builder for DDR2 and DDR3 SDRAM Controller with UniPHY, QDR II and QDR II SRAM Controller with UniPHY, and the RLDRAM II Controller with UniPHY.

For DDR2 and DDR3 SDRAM Controller, perform the following steps to enable UniPHY-based memory IP support in SOPCBuilder:

1. On the Controller Settings tab in the DDR2 and DDR3 SDRAM Controller with UniPHY parameter editor, turn on Generate power-of-2 data bus widths for SOPC Builder.
2. On the Controller Settings tab in the DDR2 and DDR3 SDRAM Controller with UniPHY parameter editor, turn on Generate SOPC Builder compatible resets.
3. After generating your external memory interface IP system, open your .sopc file in a text editor. In the .sopc file, locate lines similar to the following (where <instance_name> is the instance name of your IP core): //reset sources mux, which is an e_mux assign reset_n_sources = ~(~reset_n | 0 | 0 | ~<instance_name>_avl_resetrequest_n_from_sa| ~<instance_name>_avl_resetrequest_n_from_sa); Replace each occurrence of ~<instance_name>_avl_resetrequest_n_from_sa with 0 (zero), so that the above snippet becomes as follows: //reset sources mux, which is an e_mux assign reset_n_sources = ~(~reset_n | 0 | 0 | 0 | 0);
4. Manually reconnect the UniPHY reset inputs (global_reset_n and soft_reset_n) in the SOPC Builder-generated top-level file (system.v), as follows: .global_reset_n (reset_n_sources), .soft_reset_n (reset_n_sources),

For QDR II and QDR II SRAM Controller, perform the following steps to enable UniPHY-based memory IP support in SOPCBuilder:

1. On the Controller Settings tab in the QDR II and QDR II SRAM Controller with UniPHY parameter editor, turn on Generate power-of-2 data bus widths for SOPC Builder.
2. On the Controller Settings tab in the QDR II and QDR II SRAM Controller with UniPHY parameter editor, turn on Generate SOPC Builder compatible resets.
3. After generating your external memory interface IP system, open your .sopc file in a text editor. In the .sopc file, locate lines similar to the following (where <instance_name> is the instance name of your IP core): //reset sources mux, which is an e_mux assign reset_n_sources = ~(~reset_n | 0 | 0 | ~<instance_name>_avl_resetrequest_n_from_sa| ~<instance_name>_avl_resetrequest_n_from_sa); Replace each occurrence of ~<instance_name>_avl_resetrequest_n_from_sa with 0 (zero), so that the above snippet becomes as follows: //reset sources mux, which is an e_mux assign reset_n_sources = ~(~reset_n | 0 | 0 | 0 | 0);
4. Manually reconnect the UniPHY reset inputs (global_reset_n and soft_reset_n) in the SOPC Builder-generated top-level file (system.v), as follows: .global_reset_n (reset_n_sources), .soft_reset_n (reset_n_sources),

For RLDRAM II Controller, perform the following steps to enable UniPHY-based memory IP support in SOPCBuilder:

1. On the Controller Settings tab in the RLDRAM II Controller with UniPHY parameter editor, turn on Generate power-of-2 data bus widths for SOPC Builder.
2. On the Controller Settings tab in the RLDRAM II Controller with UniPHY parameter editor, turn on Generate SOPC Builder compatible resets.
3. After generating your external memory interface IP system, open your .sopc file in a text editor. In the .sopc file, locate lines similar to the following (where <instance_name> is the instance name of your IP core): //reset sources mux, which is an e_mux assign reset_n_sources = ~(~reset_n | 0 | 0 | ~<instance_name>_avl_resetrequest_n_from_sa| ~<instance_name>_avl_resetrequest_n_from_sa); Replace each occurrence of ~<instance_name>_avl_resetrequest_n_from_sa with 0 (zero), so that the above snippet becomes as follows: //reset sources mux, which is an e_mux assign reset_n_sources = ~(~reset_n | 0 | 0 | 0 | 0);
4. Manually reconnect the UniPHY reset inputs (global_reset_n and soft_reset_n) in the SOPC Builder-generated top-level file (system.v), as follows: .global_reset_n (reset_n_sources), .soft_reset_n (reset_n_sources),