Type: Answers

Type: Errata

Area: EMIF

Area: Intellectual Property

Fitter Error When Compiling DDR2 Designs Below 240MHz in DDR2 and DDR3 SDRAM Controller with UniPHY


For DDR2 designs operating at frequencies of 240MHz or less, the Fitter might display the error message: Can’t place Top/Bottom or Left/Right PLL.


The workaround for this issue is to turn on the Remove Duplicate Registers synthesis option.