For memory interfaces created with version 11.0 or later of the high-performance controller II (HPC II), DDR3 ODT failures can occur in simulation with Denali.
Type: Answers, Errata
Area: EMIF, Intellectual Property
There are two possible workarounds for this issue:Option 1:
alt_mem_ddrx_controller_st_top.v file and
add 1 (clk) to the equation used to derive the
2: Open the generated file
localparam CFG_READ_ODT_CHIP value to