DDR3 ODT Fails in Simulation with Denali for DDR2 and DDR3 SDRAM Controller with UniPHY and DDR3 SDRAM Controller with ALTMEMPHY IP

For memory interfaces created with version 11.0 or later of the high-performance controller II (HPC II), DDR3 ODT failures can occur in simulation with Denali.

There are two possible workarounds for this issue:Option 1: Open the alt_mem_ddrx_controller_st_top.v file and add 1 (clk) to the equation used to derive the localparams CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP and CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP.Option 2: Open the generated file <variation_name>_alt_mem_ddrx_controller_top.v and change the localparam CFG_READ_ODT_CHIP value to ‘h0 .