Critical Issue
Description
Designs generated in version 10.0SP1 and earlier may experience calibration failure due to unreliable asynchronous signal transfer from the AFI clock domain to the readcapture clock domain.
Resolution
For QDR II and QDR II SRAM Controller with UniPHY, open the design in version 10.1 of the QDR II and QDR II SRAM Controller with UniPHY and regenerate the design.
For RLDRAM II Controller with UniPHY, open the design in version 10.1 of the RLDRAM II Controller with UniPHY and regenerate the design.