Type: Answers

Type: Errata

Area: EMIF

Area: Intellectual Property



Simulation Fails with PLL Clocks Out of Synchronization for UniPHY External Memory Interfaces

Description

During simulation, the PLL clocks lose synchronization.

Workaround/Fix

To work around this issue, follow these steps:

  1. In text editor open the design file and remove the following line: coverage exclude_file
  2. In the ALTPLL MegaWizard interface, turn on Create output files using the Advanced PLL parameters and regenerate the PLL ().