Commencing with the Quartus. II software version 10.0 SP1, the clock rate specification for column and row I/Os is decreased from 150MHz to 133MHz for full-rate DDR2 IP cores on Cyclone IV E I8L devices with vcc=1.0V. This reduction in specification is due to changes associated with finalized timing models.
This issue affects all configurations.
The maximum clock rate for column and row I/Os is decreased.