Type: Answers, Errata

Area: EMIF, Intellectual Property



Selecting VHDL for QDR II and QDR II+ SRAM Controller with UniPHY or RLDRAM II Controller with UniPHY Gives a Verilog HDL IP Core

Description

The DisplayPort IP core does not assert the rx_vid_locked signal for designs in RBR mode. The receiver does not show any data.

You will not be able to test your design in RBR mode in simulation. The simulation test eventually times out after a period of time.

Workaround/Fix

To generate a VHDL IP core follow these steps:�

  1. In a text editor open� <Quartus II directory>\ip\altera\uniphy\lib\altera_uniphy_qdrii_hw.tcl.
  2. Search for the string "LANGUAGE" that appears in the following code:� append param_str ",LANGUAGE=[get_generation_property HDL_LANGUAGE]"�
  3. Change this line to the following code:� append param_str ",LANGUAGE=vhdl"
  4. Continue searching for the next occurence of the string "LANGUAGE" which appears in the following code: if {[string compare -nocase [get_generation_property HDL_LANGUAGE]� verilog] == 0} {� add_file /.v {SYNTHESIS SUBDIR}� puts "set_global_assignment -name VERILOG_FILE \[file� join $::quartus(qip_path) .v\]"� } else { add_file /.vhd {SYNTHESIS SUBDIR}� puts "set_global_assignment -name VHDL_FILE \[file join $::quartus(qip_path) .vhd\]" }�
  5. Comment out the if line, the else line, and the block of code in the conditional� section so that the code in the "else" block always executes, similar to the� following code:� # if {[string compare -nocase [get_generation_property HDL_LANGUAGE] verilog] == 0} {� # add_file /.v {SYNTHESIS SUBDIR}� # puts "set_global_assignment -name VERILOG_FILE \[file join $::quartus(qip_path) .v\]"� # } else { add_file /.vhd {SYNTHESIS SUBDIR}� puts "set_global_assignment -name VHDL_FILE \[file join� $::quartus(qip_path) .vhd\]" # }
  6. Use the MegaWizard interface to generate a UniPHY-based IP core.

To generate a Verilog HDL IP core, restore the original altera_uniphy_qdrii_hw.tcl� file.