The DQS clock buffer location for the UniPHY can cause hold time violations when placed suboptimally. The Quartus II software may suboptimally place the DQS clock buffer on a global or dual-regional clock after reentering the FPGA, so that it can be routed to the write side of the read capture FIFO buffer.
Type: Answers, Errata
Area: EMIF, Intellectual Property
Create a location assignment on the buffer to the same edge
as the memory interface (for example