This is due to hardware reset is asserted less than three clock cycles, causing reset sequence to be unable to complete and the receiver PCS reset stays constant high after reset. Users might be able to observe LED Link indicate link is down.
The situation above occurs on one of the following TSE IP core variations as below
- 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS,
- 1000BASE-X/SGMII PCS
and if the following Quartus® II version is used
- Quartus 10.1 SP1 Patch 1.77 or later
- Quartus 11.0,
- Quartus 11.0 SP1,
- Quartus 11.0 SP2,
- Quartus 11.1,
- Quartus 11.1 SP1,
- Quartus 11.1 SP2.