Type: Answers

Area: Intellectual Property


IP Product: Triple Speed Ethernet MAC

Why does the Triple Speed Ethernet (TSE) IP Core s LED Link indicate that link is down after reset?

Description

This is due to hardware reset is asserted less than three clock cycles, causing reset sequence to be unable to complete and the receiver PCS reset stays constant high after reset. Users might be able to observe LED Link indicate link is down.

The situation above occurs on one of the following TSE IP core variations as below

  • 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS,
  • 1000BASE-X/SGMII PCS

and if the following Quartus® II version is used

  • Quartus 10.1 SP1 Patch 1.77 or later
  • Quartus 11.0,
  • Quartus 11.0 SP1,
  • Quartus 11.0 SP2,
  • Quartus 11.1,
  • Quartus 11.1 SP1,
  • Quartus 11.1 SP2.

Workaround/Fix

The fix-file below ensures that reset sequence is complete and receiver PCS reset does not stay constant high after reset.

Please unzip the zip file into triple_speed_ethernet-library, and recompile the Triple Speed Ethernet project.

ResetSequencer_Fix_for_TSE_10.1_Patch_1.77_or_later.zip

This issue will be fixed in future release.