Due to a problem in the Quartus® II software version 11.0 and later, you may see this error during synthesis if your design includes a Qsys system with an On-Chip FIFO Memory component that uses an Avalon® Streaming interface.
To work around this problem, edit the Verilog HDL file for the top-level design created by Qsys containing the On-Chip FIFO Memory. Remove or comment out the connection for the avalonst_sink_empty port. For example, remove or comment out the following port connection on the On-Chip FIFO Memory instance:
This issue is fixed beginning with the Quartus II software version 12.0.