Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Memory Controller

What files do I need to update in my UniPHY controller when OCT sharing is enabled?

Description

When creating UniPHY controllers with OCT sharing enabled, you must have one UniPHY controller specified as the OCT master and the others defined as OCT slaves.

If you generate a QDR II or RLDRAM II UniPHY controller with OCT slave enabled, you must modify the pin assignment script to allow the fitter to correctly resolve the OCT termination block name in the OCT master core.

To modify the pin assignment script for QDR II or RLDRAM II OCT slaves, follow these steps:

1. In a text editor, open your core's pin assignments script file, as follows:

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For systems generated with the MegaWizard Plug-In Manager:

Open the <IP core name>/<IP core name>_pin_assignments.tcl file. (This is incorrectly specified in the External Memory Interface Handbook version 11.1, November 2011).

.

For systems generated with Qsys or SOPC Builder:

Open the <HDL Path>/<submodules>/<master_corename>_pin_assignments.tcl file.

2. Search for the following line:

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set ::master_corename "_MASTER_CORE_"

3. Replace _MASTER_CORE_ with the instance name of the UniPHY master to which the slave is connected. Even though the variable is named master_corename, the master instance name must be used. The name to use is the same as that for the instance name in the <IP core name>_all_pins.txt file that is automatically generated when the master <IP core name>_pin_assignments.tcl script runs.