You may encounter this warning message when compiling UniPHY based controller in Quartus® II software version 11.1SP2.
In Stratix® V devices, only certain PLL output counters have matched skew and other output counters can have up to maximum of 250 to 300ps of skew. This warning message is caused due to PHY clocks being placed on to the counters with high skew. Currently there is no mechanism to ensure that the PLL counters driving PHY clocks are placed into the low skew locations.
You will not see the warning message in Quartus II software versions before 11.1SP2 and this skew between the counters is not captured by TimeQuest, so it is possible to have up to 300ps of clock uncertainty that is not accounted for by TimeQuest.
This issue affects any transfers between PHY clock driven flip-flops and flip-flops driven by another clock.
Key concerns are
- Core to periphery transfers (GCLK-PHYCLK)
- Any half-rate to full-rate transfer (PHYCLK-PHYCLK)
For each PLL, low skew counters are the 1st four and last four counters. Counters 0-3 and 14-17 are matched together i.e. counters 0 and 5 have a large relative skew, as do counters 0 and 16 but 0 and 2 do not, nor do 15 and 16.