Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does the DDR3 hard memory controller with UniPHY return invalid read data after the individual multi-port front end port is reset?

Description

Due to a problem in the Quartus® II software, the DDR3 hard memory controller with UniPHY may return invalid read data after an individual multi-port front end (MPFE) port is reset (mp_*reset_n*), without resetting the whole controller (ctl_reset_n/soft_reset_n/global_reset_n). This problem occurs because the write address register for the read data FIFO is not being reset together with the read address register. This mismatch leads to read addresses pointing to the wrong location of the read data returned by the controller.

Workaround/Fix

This problem will be fixed in a future version of the Quartus II software.