Device Family: Intel® Arria® 10 SX

Type: Answers

Area: Embedded

Area: EMIF



Can unused HPS EMIF pins be used as FPGA GPIOs?

Description

Yes, unused HPS EMIF pins can be used as FPGA GPIO's, but there are some restrictions.

The Quartus® Prime software version 15.1.1 and earlier do not check for these restrictions.  You must manually ensure that if there is an HPS EMIF in the system, the I/O banks are used exclusively as follows.

Workaround/Fix

Arria 10 SoC devices have 3 modular I/O banks to connect the HPS to an SDRAM (2K, 2J, and 2I) through a dedicated HPS EMIF.

  • Each bank has 4 I/O lanes that correspond to:
    • Lane 3: IO[47:36]    
    • Lane 2: IO[35:24]    
    • Lane 1: IO[23:12]    
    • Lane 0: IO[11:0]
  • Lane 3 of Bank 2K is used to connect to the ECC signals of the SDRAM.
    • Unused pins in this lane can be used as FPGA inputs only, regardless of whether or not ECC is implemented in the system.
    • When there is no HPS EMIF in the system each bank can be used entirely as FPGA GPIO
  • Lanes 2, 1, and 0 of Bank 2K are used to connect to the address and command signals of the SDRAM.
    • Unused pins in these lanes can be used as FPGA inputs or outputs.
  • When using 16-bit data widths, unused pins in the 2 lanes of Bank 2J used for data can be used as inputs only. The pins in the remaining 2 lanes can be used as FPGA inputs or outputs. 
  • When using 32-bit data widths, unused pins Bank 2J can be used as inputs only.
  • Bank 2I may be used to connect to Data pins [63:32] of the SDRAM.
    • If the memory is only 16 or 32 bits, these pins may be used for FPGA GPIO.

 

A patch is being created for the Quartus Prime software version 15.1 that will generate errors if the conditions listed above are violated.

  • The patch will be added here once released.

 

The patch above is also scheduled to be added to a future version of the Quartus Prime software.