Device Family: Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Can the address pins be swapped on my DDR2 or DDR3 UniPHY controller?


No, the address (mem_a) and bank address (mem_ba) signals are used for programming the mode registers in the DDR2 or DDR3 memory device during initialization. Swapping around the address pins would result in an incorrect setting to the mode registers in the memory device.