Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Is there an issue with DDR2/DDR3 SDRAM High Performance Contoller II with local to memory address mapping?

Description

Yes, there is an issue with option "Local-to-Memory Address Mapping" in Quartus II software and IP version 10.1SP1 and earlier. Even when this option is set to "CHIP-ROW-BANK-COL", address mapping in functionality shows up to be "CHIP-BANK-ROW-COL" when you have Configuration and Status Register (CSR) option enabled in the IP.

There are two workarounds for this issue:

1. Make manual RTL changes to the code

  • Open file alt_ddrx_csr.v and go to line 531 that specifies the default for ADDR_ORDER.
  • Change the default from 2'b01 to 2'b00.
  • Search for ADDR_ORDER again in the file and find where ADDR_ORDER = 1.
  • Change this value from 1 to 0.

2. Change the value of ADDR_ORDER through CSR port. Refer to DDR3 Controller with Altmemphy IP User Guide (PDF) Table 7-13 for more information on the register mapping that programs ADDR_ORDER.