Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

** Warning nofile(37) in protected region.

Description

You may experience the above warning while simulating a VHDL-based DDR3 UniPHY memory controller with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog and SystemVerilog submodules are encrypted to allow simulation with a single-language simulator. If a warning occurs in the encrypted fileset, a cryptic message like the one above will be generated.

Workaround/Fix

Make sure the DDR3 files are being compiled in the order specified in the msim_setup.tcl file in the <variation_name>_sim directory. Any files compiled out-of-order may result in the above warning.

If you still see the above warning after compiling the files in the correct order, you will need to create a Verilog-based DDR3 UniPHY memory controller and use the unencrypted Verilog and SystemVerilog files in place of the encrypted fileset to isolate the source of the warning. This requires a dual-language simulator like ModelSim SE.