Make sure the DDR3 files are being compiled in the order specified in the msim_setup.tcl file in the <variation_name>_sim directory. Any files compiled out-of-order may result in the above warning.
If you still see the above warning after compiling the files in the correct order, you will need to create a Verilog-based DDR3 UniPHY memory controller and use the unencrypted Verilog and SystemVerilog files in place of the encrypted fileset to isolate the source of the warning. This requires a dual-language simulator like ModelSim SE.