Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Critical Warning: PLL clock *|divclk not driven by a dedicated clock pin or neighboring PLL source.

Description

You may see the above critical warning when the PLL reference clock to a UniPHY-based memory controller is sourced from a global clock routing resource. The global routing resource will add extra jitter to the clock signals based on the quantity and toggling frequency of the signals routed nearby. It is not possible to determine the amount of extra jitter seen by the global routing resource, and therefore, cannot be accounted for during timing analysis.

It is recommended that you use a dedicated clock input pin that is directly routed to the memory controller reference clock input.